X9470V24I【PDF 21/24 页】IC BIAS CTRLR RF PA 24-TSSOP

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X9470

WRITE OPERATIONS

Byte Write

For a write operation, the device requires the Slave

Address Byte and the Word Address Bytes. This gives

the master access to any one of the words in the

array. Upon receipt of each address byte, the X9470

responds with an acknowledge. After receiving the

address bytes the X9470 awaits the eight bits of data.

After receiving the 8 data bits, the X9470 again

responds with an acknowledge. The master then ter-

minates the transfer by generating a stop condition.

The X9470 then begins an internal write cycle of the

data to the nonvolatile memory. During the internal

write cycle, the device inputs are disabled, so the

device will not respond to any requests from the master.

The SDA output is at high impedance. See Figure 12.

A write to a protected block of memory is ignored, but

will still receive an acknowledge. At the end of the

write command, the X9470 will not initiate an internal

write cycle, and will continue to ACK commands.

Stops and Write Modes

Stop conditions that terminate write operations must be

sent by the master after sending at least 1 full data byte

and it’s associated ACK signal. If a stop is issued in the

middle of a data byte, or before 1 full data byte + ACK is

sent, then the X9470 resets itself without performing the

write. The contents of the array are not affected.

Acknowledge Polling

Disabling of the inputs during nonvolatile write cycles

can be used to take advantage of the typical 5ms write

cycle time. Once the stop condition is issued to indi-

cate the end of the master’s byte load operation, the

X9470 initiates the internal nonvolatile write cycle.

Acknowledge polling can begin immediately. To do

this, the master issues a start condition followed by the

Slave Address Byte for a write or read operation. If the

X9470 is still busy with the nonvolatile write cycle then

no ACK will be returned. When the X9470 has com-

pleted the write operation, an ACK is returned and the

host can proceed with the read or write operation.

Refer to the flow chart in Figure 15.

21

READ OPERATIONS

There are three basic read operations: Current

Address Read, Random Read, and Sequential Read.

Current Address Read

Internally the X9470 contains an address counter that

maintains the address of the last word read incre-

mented by one. Therefore, if the last read was to

address n, the next read operation would access data

from address n+1. On power-up, the address is initial-

ized to 0h. In this way, a current address read immedi-

ately after the power-on reset can download the entire

contents of memory starting at the first location. Upon

receipt of the Slave Address Byte with the R/W bit set

to one, the X9470 issues an acknowledge, then trans-

mits eight data bits. The master terminates the read

operation by not responding with an acknowledge dur-

ing the ninth clock and issuing a stop condition. Refer

to Figure 13 for the address, acknowledge, and data

transfer sequence.

FN8204.0

March 8, 2005

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